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Features
* Utilizes the ARM7TDMITM ARM Thumb Processor Core
- High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE (In-Circuit Emulation) 8K Bytes Internal SRAM Fully-programmable External Bus Interface (EBI) - Maximum External Address Space of 128M Bytes - 8 Chip Selects - Software Programmable 8/16-bit External Databus 8-level Priority, Individually Maskable, Vectored Interrupt Controller - 7 External Interrupts, Including a High-priority, Low-latency Interrupt Request 58 Programmable I/O Lines 6-channel 16-bit Timer/Counter - 6 External Clock Inputs and 2 Multi-purpose I/O Pins per Channel 3 USARTs Master/Slave SPI Interface - 8-bit to 16-bit Programmable Data Length - 4 External Slave Chip Selects Programmable Watchdog Timer 8-channel 10-bit ADC 2-channel 10-bit DAC Clock Generator with On-chip Main Oscillator and PLL for Multiplication - 3 to 20 MHz Frequency Range Main Oscillator Real-time Clock with On-chip 32 kHz Oscillator - Battery Backup Operation and External Alarm 8-channel Peripheral Data Controller for USARTs and SPIs Advanced Power Management Controller (APMC) - Normal, Wait, Slow, Standby and Power-down modes IEEE 1149.1 JTAG Boundary-scan on all Digital Pins Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at VDDCORE = 3.0V, 85C 2.7V to 3.6V Core Operating Range, 2.7V to 5.5V I/O Operating Range 2.7V to 3.6V Analog Operating Range 1.8V to 3.6V Backup Battery Operating Range 2.7V to 3.6V Oscillator and PLL Operating Range -40C to +85C Temperature Range Available in a 176-lead TQFP or 176-ball BGA Package
* *
* * * * * * * * * * * * * * * * * * * *
AT91 ARM(R) Thumb(R) Microcontrollers AT91M55800A Summary
Description
The AT91M55800A is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The fully programmable External Bus Interface provides a direct connection to off-chip memory in as fast as one clock cycle for a read or write operation. An eight-level priority vectored interrupt controller in conjunction with the peripheral data controller significantly improve the real-time performance of the device. The device is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip SRAM, a wide range of peripheral functions, analog interfaces and low-power oscillators on a monolithic chip, the Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and costeffective solution to many ultra low-power applications.
Rev. 1745CS-ATARM-05/02
Note: This is a summary document. A complete document 1 is available on our web site at www.atmel.com.
Pin Configurations
Table 1. Pin Configuration for 176-lead TQFP Package
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
AT91M55800A
GND GND NCS0 NCS1 NCS2 NCS3 NLB/A0 A1 A2 A3 A4 A5 A6 A7 VDDIO GND A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 VDDIO GND A20 A21 A22 A23 D0 D1 D2 D3 D4 D5 D6 D7 VDDCORE VDDIO
Pin
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
AT91M55800A
GND GND D8 D9 D10 D11 D12 D13 D14 D15 PB19/TCLK0 PB20/TIOA0 PB21/TIOB0 PB22/TCLK1 VDDIO GND PB23/TIOA1 PB24/TIOB1 PB25/TCLK2 PB26/TIOA2 PB27/TIOB2 PA0/TCLK3 PA1/TIOA3 PA2/TIOB3 PA3/TCLK4 PA4/TIOA4 PA5/TIOB4 PA6/TCLK5 VDDIO GND PA7/TIOA5 PA8/TIOB5 PA9/IRQ0 PA10/IRQ1 PA11/IRQ2 PA12/IRQ3 PA13/FIQ PA14/SCK0 PA15/TXD0 PA16/RXD0 PA17/SCK1 PA18/TXD1/NTRI VDDCORE VDDIO
Pin
89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
AT91M55800A
GND GND PA19/RXD1 PA20/SCK2 PA21/TXD2 PA22/RXD2 PA23/SPCK PA24/MISO PA25/MOSI PA26/NPCS0/NSS PA27/NPCS1 PA28/NPCS2 PA29/NPCS3 VDDIO GND VDDPLL XIN XOUT GNDPLL PLLRC VDDBU(2) XIN32(2) XOUT32(2) NRSTBU(2) GNDBU(2) WAKEUP(2) SHDN(2) GNDBU(2) VDDA(1) AD0(1) AD1(1) AD2(1) AD3(1) AD4(1) AD5(1) AD6(1) AD7(1) ADVREF(1) DAVREF(1) DA0(1) DA1(1) GNDA(1) VDDCORE VDDIO
Pin
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
AT91M55800A
GND GND NCS4 NCS5 NCS6 NCS7 PB0 PB1 PB2 PB3/IRQ4 PB4/IRQ5 PB5 PB6/AD0TRIG PB7/AD1TRIG VDDIO GND PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 NWDOVF MCKO VDDIO GND PB18/BMS JTAGSEL TMS TDI TDO TCK NTRST NRST NWAIT NOE/NRD NWE/NWR0 NUB/NWR1 VDDCORE VDDIO
Notes:
1. Analog pins 2. Battery backup pins
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Table 2. Pin Configuration for 176-ball BGA Package
Pin
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
AT91M55800A
NCS1 NWAIT NRST NTRST PB18/BMS NWDOVF PB16 PB12 PB10 PB9 PB8 NCS7 NCS6 GND DAVREF NCS2 NUB/NWR1 NWE/NWR0 NOE/NRD TD0 TDI PB17 PB11 PB7/AD1TRIG PB3/IRQ4 PB2 NCS5 NCS4 DA1 GNDA
Pin
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
AT91M55800A
A0/NLB NCS0 VDDIO VDDCORE TMS VDDIO MCK0 PB13 PB6/AD0TRIG VDDIO PB4/IRQ5 PB0 VDDIO DA0 ADVREF A2 A1 NCS3 GND TCK JTAGSEL GND PB15 PB14 PB5 PB1 GND VDDCORE AD7 VDDA
Pin
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
AT91M55800A
A4 A3 A5 GND - - - - - - - AD6 AD5 NRSTBU GNDBU A10 A7 VDDIO A6 - - - - - - - GND AD4 VDDBU XOUT32
Pin
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15
AT91M55800A
A12 A9 A8 GND - - - - - - - AD3 AD2 GND XIN32 A15 A14 A13 A11 - - - - - - - AD1 AD0 WAKEUP GND
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Table 2. Pin Configuration for 176-ball BGA Package (Continued)
Pin
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15
AT91M55800A
A17 A18 VDDIO A16 - - - - - - - PA29/NPCS3 SHDN VDDPLL PLLRC A19 A22 A21 GND - - - - - - - PA28/NPCS2 VDDIO PA27/NPCS1 GNDPLL
Pin
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15
AT91M55800A
A20 A23 D0 D1 - - - - - - - PA25/MOSI PA22RXD2 PA26/NPCS0/NSS XOUT D2 D3 VDDCORE GND GND PB21/TIOB0 GND PB27/TIOB2 PA0/TCLK3 GND PA23/SPCK GND PA21/TXD2 PA24/MISO XIN
Pin
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
AT91M55800A
D4 D6 VDDIO D14 PB19/TCLK0 VDDIO PB25/TCLK2 PA1/TIOA3 VDDIO PA8/TIOB5 PA9/IRQ0 VDDCORE VDDIO PA19/RXD1 GND D5 D7 D8 D9 D15 PB22/TCLK1 PB26/TIOA2 PA2/TIOB3 PA7/TIOA5 PA10/IRQ1 PA11/IRQ2 PA13/FIQ PA17SCK1 PA18/TXD1/NTRI PA20/SCK2
Pin
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
AT91M55800A
D10 D11 D12 D13 PB20/TIOA0 PB23/TIOA1 PB24/TIOB1 PA3/TCLK4 PA4/TIOA4 PA5/TIOB4 PA6/TCLK5 PA12/IRQ3 PA14/SCK0 PA15/TXD0 PA16/RXD0
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Figure 1. 176-lead TQFP Pinout
132 133 89 88
176
45 1 44
Figure 2. 176-ball BGA Pinout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
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Pin Description
Table 3. Pin Description
Module Name A0 - A23 D0 - D15 NCS0 - NCS7 NWR0 NWR1 NRD EBI NWE NOE NUB NLB NWAIT BMS IRQ0 - IRQ5 AIC FIQ TCLK0 - TCLK5 Timer TIOA0 - TIOA5 TIOB0 - TIOB5 SCK0 - SCK2 USART TXD0 - TXD2 RXD0 - RXD2 SPCK MISO SPI MOSI NSS NPCS0 - NPCS3 PA0 - PA29 PIO PB0 - PB27 WD NWDOVF AD0 - AD7 AD0TRIG ADC AD1TRIG ADVREF DA0 - DA1 DAC DAVREF Analog reference Analog ref - ADC1 external trigger Analog reference Analog output channels 0 - 1 Input Analog ref Analog out - - - PIO-controlled after reset Parallel I/O port B Watchdog timer overflow Analog input channels 0 - 7 ADC0 external trigger I/O Output Analog in Input - Low - - PIO-controlled after reset Input after reset Open drain Fast external interrupt request Timer external clock Multipurpose timer I/O pin A Multipurpose timer I/O pin B External serial clock Transmit data output Receive data input SPI clock Master in slave out Master out slave in Slave select Peripheral chip select Parallel I/O port A Input Input I/O I/O I/O Output Input I/O I/O I/O Input Output I/O - - - - - - - - - - Low Low - PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Input after reset Write enable Output enable Upper byte-select Lower byte-select Wait input Boot mode select External interrupt request Output Output Output Output Input Input Input Low Low Low Low Low - - Sampled during reset PIO-controlled after reset Used in Byte-select option Used in Byte-select option Used in Byte-select option Used in Byte-select option Function Address bus Data bus Chip select Lower byte 0 write signal Lower byte 1 write signal Read signal Type Output I/O Output Output Output Output Active Level - - Low Low Low Low Used in Byte-write option Used in Byte-write option Used in Byte-write option Comments
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Table 3. Pin Description (Continued)
Module Name XIN XOUT PLLRC Clock XIN32 XOUT32 MCKO WAKEUP APMC SHDN NRST Reset NRSTBU NTRI JTAGSEL TMS JTAG/ICE TDI TDO TCK NTRST VDDA GNDA VDDBU GNDBU Power VDDCORE VDDIO VDDPLL GND GNDPLL Shutdown request Hardware reset input Hardware reset input for battery part Tri-state mode select Selects between ICE and JTAG mode Test mode select Test data input Test data output Test clock Test reset input Analog power Analog ground Power backup Ground backup Digital core power Digital I/O power Main oscillator and PLL power Digital ground PLL ground Output Input Input Input Input Input Input Output Input Input Analog pwr Analog gnd Power Ground Power Power Power Ground Ground - Low Low Low - - - - - Low - - - - - - - - - Schmidt trigger, internal pull-up Schmidt trigger, internal pull-up Schmidt trigger, internal pull-up Schmidt trigger, internal pull-up Tri-state after backup reset Schmidt trigger Schmidt trigger Sampled during reset 32 kHz oscillator input 32 kHz oscillator output System clock Wakeup request Input Output Output Input - - - - Function Main oscillator input Main oscillator output RC filter for PLL Type Input Output Input Active Level - - - Comments
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Block Diagram
Figure 3. AT91M55800A
JTAGSEL NTRST TMS TDO TDI TCK JTAGSEL Embedded ICE Reset NRST
ARM7TDMI Core
PB0 PB1 PB2 PB5 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB3/IRQ4 PB4/IRQ5 PA9/IRQ0 PA10/IRQ1 PA11/IRQ2 PA12/IRQ3 PA13/FIQ PA14/SCK0 PA15/TXD0 PA16/RXD0 PA17/SCK1 PA18/TXD1/NTRI PA19/RXD1 PA20/SCK2 PA21/TXD2 PA22/RXD2 PA23/SPCK PA24/MISO PA25/MOSI PA26/NPCS0/NSS PA27/NPCS1 PA28/NPCS2 PA29/NPCS3 JTAG
VDDIO, VDDCORE GND ASB D0 - D15 A1 - A23 EBI: External Bus Interface
P I O B
Internal RAM 8K Bytes
ASB Controller
A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NWAIT NCS0 - NCS7
AIC: Advanced Interrupt Controller
AMBA Bridge EBI User Interface PB18/BMS 2 PDC Channels APB 2 PDC Channels 2 PDC Channels PIOB Controller TC: Timer Counter Block 0 TC0 TC1 TC2 P I O B PB19/TCLK0 PB22/TCLK1 PB25/TCLK2 PB20/TIOA0 PB21/TIOB0 PB23/TIOA1 PB24/TIOB1 PB26/TIOA2 PB27/TIOB2 PA0/TCLK3 PA3/TCLK4 PA6/TCLK5 P I O A PA1/TIOA3 PA2/TIOB3 PA4/TIOA4 PA5/TIOB4 PA7/TIOA5 PA8/TIOB5 VDDPLL
USART0
USART1 P I O A
USART2
SPI: Serial Peripheral Interface
2 PDC Channels
TC: Timer Counter Block 1 TC3
PIOA Controller
TC4 TC5
NWDOVF
WD: Watchdog Timer
VDDA DA0 DAVREF DA1 PB6/AD0TRIG AD0 AD1 AD2 AD3 ADVREF AD4 AD5 AD6 AD7 PB7/AD1TRIG
Chip ID
Clock Generator PLL
MCKO XIN 16 MHz XOUT PLLRC GNDPLL VDDBU
DAC0
DAC1 APMC: Advanced Power Management Controller
4-Channel ADC0
SHDN WAKEUP
4-Channel ADC1 RTC: Real Time Clock NRSTBU XIN32 32.768 kHz XOUT32 GNDBU
Analog GNDA
Battery Backup
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Architectural Overview
The AT91M55800A microcontroller integrates an ARM7TDMI with its embedded ICE interface, memories and peripherals. Its architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the on-chip 32-bit memories, the External Bus Interface (EBI) and the AMBATM Bridge. The AMBA Bridge drives the APB, which is designed for accesses to on-chip peripherals and optimized for low power consumption. The AT91M55800A microcontroller implements the ICE port of the ARM7TDMI processor on dedicated pins, offering a complete, low cost and easy-to-use debug solution for target debugging.
Memory
The AT91M55800A microcontroller embeds 8K bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. The AT91M55800A microcontroller features an External Bus Interface (EBI), which enables connection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the early read protocol, enabling faster memory accesses than standard memory interfaces.
Peripherals
The AT91M55800A microcontroller integrates several peripherals, which are classified as system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can be programmed with a minimum number of instructions. The peripheral register set is composed of control, mode, data, status and enable/disable/status registers. An on-chip, 8-channel Peripheral Data Controller (PDC) transfers data between the onchip USARTs/SPI and the on and off-chip memories without processor intervention. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART and of the SPI. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes. As a result, the performance of the microcontroller is increased and the power consumption reduced.
System Peripherals
The External Bus Interface (EBI) controls the external memory and peripheral devices via an 8- or 16-bit data bus and is programmed through the APB. Each chip select line has its own programming register. The Advanced Power Management Controller (APMC) optimizes power consumption of the product by controlling the clocking elements such as the oscillators and the PLL, system and user peripheral clocks, and the power supplies. The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal peripherals and the eight external interrupt lines (including the FIQ), to provide an interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and, using the auto-vectoring feature, reduces the interrupt latency time. The Real-time Clock (RTC) peripheral is designed for very low power consumption, and combines a complete time-of-day clock with alarm and a two-hundred year Gregorian calendar, complemented by a programmable periodic interrupt. The Parallel Input/Output Controllers (PIOA and PIOB) control the 58 I/O lines. They enable the user to select specific pins for on-chip peripheral input/output functions, and
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general-purpose input/output signal pins. The PIO controllers can be programmed to detect an interrupt on a signal change from each line. The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in a deadlock. The Special Function (SF) module integrates the Chip ID and Reset Status registers. User Peripherals Three USARTs, independently configurable, enable communication at a high baud rate in synchronous or asynchronous mode. The format includes start, stop and parity bits and up to 8 data bits. Each USART also features a Timeout and a Time Guard Register, facilitating the use of the two dedicated Peripheral Data Controller (PDC) channels. The six 16-bit Timer/Counters (TC) are highly programmable and support capture or waveform modes. Each TC channel can be programmed to measure or generate different kinds of waves, and can detect and control two input/output signals. Each TC also has three external clock signals. The SPI provides communication with external devices in master or slave mode. It has four external chip selects which can be connected to up to 15 devices. The data length is programmable, from 8- to 16-bit. The two identical 4-channel 10-bit analog-to-digital converters (ADC) are based on a Successive Approximation Register (SAR) approach. The two identical single-channel 10-bit digital-to-analog converters (DAC).
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Associated Documentation
Table 4. Associated Documentation
Product Information Internal architecture of processor ARM/Thumb instruction sets Embedded in-circuit-emulator External memory interface mapping Peripheral operations Peripheral user interfaces AT91M55800A DC characteristics Power consumption Thermal and reliability considerations AC characteristics Product overview Ordering information Packaging information Soldering profile Document Title ARM7TDMI (Thumb) Datasheet
AT91M55800A Datasheet
AT91M55800A Electrical Characteristics
AT91M55800A Summary Datasheet (this document)
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Product Overview
Power Supplies
The AT91M55800A has 5 kinds of power supply pins: * * * * * VDDCORE pins, which power the chip core VDDIO pins, which power the I/O Lines VDDPLL pins, which power the oscillator and PLL cells VDDA pins, which power the analog peripherals ADC and DAC VDDBU pins, which power the RTC, the 32768 Hz oscillator and the Shut-down Logic of the APMC
VDDIO and VDDCORE are separated to permit the I/O lines to be powered with 5V, thus resulting in full TTL compliance. The following ground pins are provided: * * * * GND for both VDDCORE and VDDIO GNDPLL for VDDPLL GNDA for VDDA GNDBU for VDDBU
All of these ground pins must be connected to the same voltage (generally the board electric ground) with wires as short as possible. GNDPLL, GNDA and GNDBU are provided separately in order to allow the user to add a decoupling capacitor directly between the power and ground pads. In the same way, the PLL filter resistor and capacitors must be connected to the device and to GNDBU with wires as short as possible. Also, the external load capacitances of the main oscillator crystal and the 32768 Hz crystal must be connected respectively to GNDPLL and to GNDBU with wires as short as possible. The main constraints applying to the different voltages of the device are: * * * VDDBU must be lower than or equal to VDDCORE VDDA must be higher than or equal to VDDCORE VDDCORE must be lower than or equal to VDDIO
The nominal power combinations supported by the AT91M55800A are described in the following table: Table 5. Nominal Power Combinations
VDDIO 3V 3.3V 5V VDDCOR E 3V 3.3V 3.3V VDDA 3V 3.3V 3.3V VDDPLL 3V 3.3V 3.3V VDDBU 3V 3.3V 3.3V Maximum Operating Frequency 33 MHz 33 MHz 33 MHz
Input/Output Considerations
After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the AT91M55800A microcontroller be held at valid logic levels to minimize the power consumption.
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Master Clock
Master Clock is generated in one of the following ways, depending on programming in the APMC registers: * * From the 32768 Hz low-power oscillator that clocks the RTC The on-chip main oscillator, together with a PLL, generate a software-programmable main clock in the 500 Hz to 33 MHz range. The main oscillator can be bypassed to allow the user to enter an external clock signal.
The Master Clock (MCK) is also provided as an output of the device on the MCKO pin, whose state is controlled by the APMC module.
Reset
Reset restores the default states of the user interface registers (defined in the user interface of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address zero. Aside from the program counter, the ARM7TDMI registers do not have defined reset states. NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. At reset, the source of MCK is the Slow Clock (32768 Hz crystal), and the signal presented on MCK must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST, to ensure correct operation. The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the BMS and NTRI pins are not sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority.
NRST Pin
Watchdog Reset
Emulation Functions
Tri-state Mode The AT91M55800A provides a Tri-state Mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In Tri-state Mode, all the output pin drivers of the AT91M55800A microcontroller are disabled. To enter Tri-state Mode, the NTRI pin must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation the NTRI pin must be held high during reset, by a resistor of up to 400K Ohm. NTRI is multiplexed with I/O line PA18 and USART 1 serial data transmit line TXD1. Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is connected to a device not including this pull-up, the user must make sure that a high level is tied on NTRI while NRST is asserted. JTAG/ICE Debug Mode ARM Standard Embedded In-Circuit Emulation is supported via the JTAG/ICE port. It is connected to a host computer via an external ICE Interface. The JTAG/ICE debug mode is enabled when JTAGSEL is low. In ICE Debug Mode the ARM Core responds with a non-JTAG chip ID which identifies the core to the ICE system. This is not JTAG compliant.
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IEEE 1149.1 JTAG Boundaryscan
JTAG Boundary-scan is enabled when JTAGSEL is high. The functions SAMPLE, EXTEST and BYPASS are implemented. There is no JTAG chip ID. The Special Function module provides a chip ID which is independent of JTAG. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed (NRST and NTRST) after JTAGSEL is changed.
Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces: * * * Internal memories in the four lowest megabytes Middle space reserved for the external devices (memory or peripherals) controlled by the EBI Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only. Internal Memories The AT91M55800A microcontroller integrates an 8-Kbyte primary SRAM bank. This memory bank is mapped at address 0x0 (after the remap command), allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. The rest of the bank can be used for stack allocation (to speed up context saving and restoring), or as data and program storage for critical algorithms. All internal memory is 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones. The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the type of boot memory (see Table 5). The BMS pin is multiplexed with the I/O line PB18 that can be programmed after reset like any standard PIO line. Table 6. Boot Mode Select
BMS 1 0 Boot Mode External 8-bit memory on NCS0 External 16-bit memory on NCS0
Boot Mode Select
Remap Command
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91M55800A microcontroller uses a remap command that enables switching between the boot memory and the internal RAM bank addresses. The remap command is accessible through the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if access to the other external devices (connected to chip selects 1 to 7) is required. The remap operation can only be changed back by an internal reset or an NRST assertion.
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Abort Control The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is asserted when accessing an undefined address in the EBI address space. No abort is generated when reading the internal memory or by accessing the internal peripherals, whether the address is defined or not. External Bus Interface The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0 0000. It generates the signals that control access to the external devices, and can configure up to eight 16-Mbyte banks. In all cases it supports byte, half-word and word aligned accesses. For each of these banks, the user can program: * * * * Number of wait states Number of data float times (wait time after the access is finished to prevent any bus contention in case the device is too long in releasing the bus) Data bus width (8-bit or 16-bit) With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16bit memory (Byte-write Access mode).
The External Bus Interface features also the Early Read Protocol, configurable for all the devices, that significantly reduces access time requirements on an external device.
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Peripherals
The AT91M55800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus. Peripheral registers are only word accessible. Byte and half-word accesses are not supported. If a byte or a half-word access is attempted, the memory controller automatically masks the lowest address bits and generates a word access. Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address space).
Peripheral Registers
The following registers are common to all peripherals: * Control Register - write only register that triggers a command when a one is written to the corresponding position at the appropriate address. Writing a zero has no effect. Mode Register - read/write register that defines the configuration of the peripheral. Usually has a value of 0x0 after a reset. Data Registers - read and/or write register that enables the exchange of data between the processor and the peripheral. Status Register - read only register that returns the status of the peripheral. Enable/Disable/Status Registers - shadow command registers. Writing a one in the Enable Register sets the corresponding bit in the Status Register. Writing a one in the Disable Register resets the corresponding bit and the result can be read in the Status Register. Writing a bit to zero has no effect. This register access method maximizes the efficiency of bit manipulation, and enables modification of a register with a single non-interruptible instruction, replacing the costly read-modify-write operation.
* * * *
Unused bits in the peripheral registers are shown as "-" and must be written at 0 for upward compatibility. These bits read 0. Peripheral Interrupt Control The Interrupt Control of each peripheral is controlled from the status register using the interrupt mask. The status register bits are ANDed to their corresponding interrupt mask bits and the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt Controller. The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask) makes it possible to enable or disable peripheral interrupt sources with a noninterruptible single instruction. This eliminates the need for interrupt masking at the AIC or Core level in real-time and multi-tasking systems. Peripheral Data Controller An on-chip, 8-channel Peripheral Data Controller (PDC) transfers data between the onchip USARTs/SPI and the on and off-chip memories without processor intervention. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART and SPI. The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes. As a result, the performance of the microcontroller is increased and the power consumption reduced.
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AT91M55800A
System Peripherals
APMC: Advanced Power Management Controller The AT91M55800A Advanced Power Management Controller allows optimization of power consumption. The APMC enables/disables the clock inputs of most of the peripherals and the ARM core. Moreover, the main oscillator, the PLL and the analog peripherals can be put in standby mode allowing minimum power consumption to be obtained. The APMC provides the following operating modes: * * * * * RTC: Real Time Clock Normal mode: clock generator provides clock to the entire chip except the RTC. Wait mode: ARM core clock deactivated Slow Clock mode: clock generator deactivated, master clock 32 kHz Standby mode: RTC active, all other clocks disabled Power-down mode: RTC active, supply on the rest of the circuit deactivated
The AT91M55800A features a Real-time Clock (RTC) peripheral that is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred year Gregorian calendar, complemented by a programmable periodic interrupt. The time and calendar values are coded in Binary-Coded Decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields is performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/ year/century.
AIC: Advanced Interrupt Controller
The AIC has an 8-level priority, individually maskable, vectored interrupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from: * * * The external fast interrupt line (FIQ) The six external interrupt request lines (IRQ0 - IRQ5) The interrupt signals from the on-chip peripherals
The AIC is largely programmable offering maximum flexibility, and its vectoring features reduce the real-time overhead in handling interrupts. The AIC also features a spurious vector, which reduces spurious interrupt handling to a minimum, and a protect mode that facilitates the debug capabilities. PIO: Parallel I/O Controller The AT91M55800A has 58 programmable I/O lines. 13 pins are dedicated as generalpurpose I/O pins. The other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO lines are controlled by two separate and identical PIO Controllers called PIOA and PIOB. The PIO controller enables the generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins. The Watchdog is built around a 16-bit counter, and is used to prevent system lock-up if the software becomes trapped in a deadlock. It can generate an internal reset or interrupt, or assert an active level on the dedicated pin NWDOVF. All programming registers are password-protected to prevent unintentional programming. The AT91M55800A provides registers which implement the following special functions. * * Chip identification RESET status
WD: Watchdog
SF: Special Function
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User Peripherals
USART: Universal Synchronous/ Asynchronous Receiver Transmitter The AT91M55800A provides three identical, full-duplex, universal synchronous/asynchronous receiver/transmitters. Each USART has its own baud rate generator, and two dedicated Peripheral Data Controller channels. The data format includes a start bit, up to 8 data bits, an optional programmable parity bit and up to 2 stop bits. The USART also features a Receiver Timeout register, facilitating variable-length frame support when it is working with the PDC, and a Time-guard register, used when interfacing with slow remote equipment. TC: Timer/Counter The AT91M55800A features two Timer/Counter blocks that include three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation. The Timer/Counters can be used in Capture or Waveform mode, and all three counter channels can be started simultaneously and chained together. SPI: Serial Peripheral Interface The SPI provides communication with external devices in master or slave mode. It has four external chip selects that can be connected to up to 15 devices. The data length is programmable, from 8- to 16-bit. The two identical 4-channel 10-bit analog-to-digital converters (ADC) are based on a Successive Approximation Register (SAR) approach. Each ADC has 4 analog input pins, AD0 to AD3 and AD4 to AD7, digital trigger input AD0TRIG and AD1TRIG pins, and provides an interrupt signal to the AIC. Both ADCs share the analog power supply VDDA and GNDA pins, and the input reference voltage ADVREF pin. Each channel can be enabled or disabled independently, and has its own data register. The ADC can be configured to automatically enter Sleep Mode after a conversion sequence, and can be triggered by the software, the Timer/Counter, or an external signal. DAC: Digital-to-analog Converter Two identical 1-channel 10-bit digital-to-analog converters (DAC). Each DAC has an analog output pin, DA0 and DA1, and provides an interrupt signal to the AIC DA0IRQ and DA1IRQ. Both DACs share the analog power supply VDDA and GNDA pins, and the input reference DAVREF.
ADC: Analog-to-digital Converter
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AT91M55800A
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AT91M55800A
Ordering Information
Table 7. Ordering Information
Ordering Code AT91M55800A-33AI AT91M55800A-33CI Package TQFP 176 BGA 176 Temperature Operating Range Industrial (-40C to 85C)
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Packaging Information
Figure 4. 176-lead Thin Quad Flat Pack Package Drawing
aaa
bbb
PIN 1
2 S
ccc
3
ddd
R1
R2 0.25
c
c1
1 L1
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AT91M55800A
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AT91M55800A
Table 8. Common Dimensions (mm)
Symbol c c1 L L1 R2 R1 S q 1 2 3 A A1 A2 0.05 1.35 1.4 0.08 0.08 0.2 0 0 11 11 12 12 13 13 1.6 0.15 1.45 3.5 7 Min 0.09 0.09 0.45 0.6 1.00 REF 0.2 Nom Max 0.20 0.16 0.75
Tolerances of form and position aaa bbb 0.2 0.2
Table 9. Lead Count Dimensions (mm)
Pin Count 176 D/E BSC 26.0 D1/E1 BSC 24.0 b Min 0.17 Nom 0.20 Max 0.27 Min 0.17 b1 Nom 0.20 Max 0.23 e BSC 0.50
ccc 0.10
ddd 0.08
Table 10. Device and 176-lead TQFP Package Maximum Weight
2023 mg
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Figure 5. 176-ball Ball Grid Array Package Drawing
Top View
Bottom View
Symbol aaa bbb ddd eee fff ggg hhh kkk Notes:
Maximum 0.1 0.1 0.1 0.03 0.04 0.03 0.1 0.1
1. Package dimensions conform to JEDEC MO-205 2. Dimensioning and tolerancing per ASME Y14.5M-1994 3. All dimensions in mm 4. Solder Ball position designation per JESD 95-1, SPP-010 5. Primary datum Z and seating plane are defined by the spherical crowns of the solder balls
Table 11. Device and 176-ball BGA Package Maximum Weight
606 mg
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AT91M55800A
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AT91M55800A
Soldering Profile
Table 12 gives the recommended soldering profile from J-STD-20. Table 12. Soldering Profile
Convection or IR/Convection Average Ramp-up Rate (183C to Peak) Preheat Temperature 125C 25C Temperature Maintained Above 183C Time within 5C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25C to Peak Temperature 3C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0C or 235 +5/-0C 6C/sec. 6 min. max 60 sec. 215 to 219C or 235 +5/-0C 10C/sec. VPR 10C/sec.
Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235C, not 220C (IR reflow). Recommended package reflow conditions depend on package thickness and volume. See Table 13. Table 13. Recommended Package Reflow Conditions (TQFP and PBGA)(1, 2, 3)
Parameter Convection VPR IR/Convection Notes: Temperature 220 +5/-0C 215 to 219C 220 +5/-0C
1. The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. 2. By default, the package level 1 is qualified at 220C (unless 235C is stipulated). 3. The body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability.
A maximum of three reflow passes is allowed per component.
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1745CS-ATARM-05/02 0M

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